Principal Digital IC Design Engineer
Experience Level: Individual Contributor
Job Type: Full-Time
Location:
TX - Richardson, US
Requisition ID: 5778
Summary:
Qorvo is seeking a Digital Design Engineer responsible for a wide variety of Digital ASIC Design tasks.
Designs primarily interface to Analog Power Solutions, including development of State Machines, Serial Interfaces, Register Blocks, OTP Blocks, supporting Clock and Reset analog circuits, and timed enabling/switching of Analog signal paths.
This position involves the full Digital Design flow including interacting with Systems for Specification generation, Architecture development, RTL description using System Verilog, Verilog Simulation Verification via developed Test Benches, Logic Synthesis, executing a Place & Route tool and associated Static Timing Analysis, and familiarization with Scan testing.
Documentation and presentation at Design Reviews is required.
Responsibilities:
Receive Specifications from Module Architects / System Engineers – review, assess, provide feedback,
and develop a digital micro-architecture
Generate RTL to comply with specifications, both by manual development and automated generation
Create Cadence schematic database of Digital Blocks via Virtuoso
System Verilog Verification Simulations of the design by creating Test Benches at block level.
Create new Verification tests and utilize existing tests that are to be modified as needed.
Execute both RTL and Gate Simulations.
Execute Logic Synthesis
Create DFT hooks and generate test patterns
Execute remaining back-end tools – Place & Route/Static Timing Analysis, LEC, LINT, CDC, ATPG
Qualifications:
System Verilog / Verilog Language and Simulation
Scripting languages (Python, TCL, UNIX/LINUX, shell, PERL, C/C++)
Synthesis and Static Timing Analysis
Strong communication skills to interface with other teams
BSEE required, MSEE preferred
Place & Route using Cadence Virtuoso, verifying Database vs Schematics
System Verilog Assertions and Functional Coverage
Formal Verification
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